Most of the power and usefulness of today's digital IC devices can be attributed to the increasing levels of integration. More and more components (resistors, diodes, transistors, and the like) are continually being integrated into the underlying chip, or IC. The starting material for typical ICs is very high purity silicon. The material is grown as a single crystal. It takes the shape of a solid cylinder. This crystal is then sawed (like a loaf of bread) to produce wafers typically 10 to 30 cm in diameter and 250 microns thick.
The geometry of the features of the IC components are commonly defined photographically through a process known as photolithography. Very fine surface geometries can be reproduced accurately by this technique. The photolithography process is used to define component regions and build up components one layer on top of another. Complex ICs can often have many different built up layers, each layer having components, each layer having differing interconnections, and each layer stacked on top of the previous layer. The resulting topography of these complex IC's often resemble familiar terrestrial “mountain ranges”, with many “hills” and “valleys” as the IC components are built up on the underlying surface of the silicon wafer.
In the photolithography process, a mask image, or pattern, defining the various components, is focused onto a photosensitive layer using ultraviolet light. The image is focused onto the surface using the optical means of the photolithography tool, and is imprinted into the photosensitive layer. To build ever smaller features, increasingly fine images must be focused onto the surface of the photosensitive layer, i.e. optical resolution must increase. As optical resolution increases, the depth of focus of the mask image correspondingly narrows. This is due to the narrow range in depth of focus imposed by the high numerical aperture lenses in the photolithography tool. This narrowing depth of focus is often the limiting factor in the degree of resolution obtainable, and thus, the smallest components obtainable using the photolithography tool. The extreme topography of complex ICs, the “hills† and “valleys,” exaggerate the effects of decreasing depth of focus. Thus, in order to properly focus the mask image defining sub-micron geometry's onto the photosensitive layer, a precisely flat surface is desired. The precisely flat (i.e. fully planarized) surface will allow for extremely small depths of focus, and in turn, allow the definition and subsequent fabrication of extremely small components.
Chemical-mechanical polishing (CMP) is the preferred method of obtaining full planarization of a wafer. It involves removing a sacrificial layer of dielectric material using mechanical contact between the wafer and a moving polishing pad saturated with slurry. Polishing flattens out height differences, since high areas of topography (hills) are removed faster than areas of low topography (valleys). Polishing is the only technique with the capability of smoothing out topography over millimeter scale planarization distances leading to maximum angles of much less than one degree after polishing.
Prior Art FIG. 1A shows a top view of a CMP machine 100 and Prior Art FIG. 1B shows a side section view of the CMP machine 100 taken through line BB of Prior Art FIG. 1A. CMP machine 100 is fed wafers to be polished. CMP machine 100 picks up the wafers with an arm 101 and places them onto a rotating polishing pad 102. Polishing pad 102 is made of a resilient material and is textured, often with a plurality of predetermined groves, to aid the polishing process. Polishing pad 102 rotates on a platen 104, or turn table located beneath polishing pad 102, at a predetermined speed. A wafer 105 is held in place on polishing pad 102 and arm 101. The lower surface of wafer 105 rests against polishing pad 102. The upper surface of wafer 105 is against the lower surface of a wafer carrier 106 of arm 101. As polishing pad 102 rotates, arm 101 rotates wafer 105 at a predetermined rate. Arm 101 forces wafer 105 into polishing pad 102 with a predetermined amount of down force. CMP machine 100 also includes a slurry dispense arm 107 extending across the radius of polishing pad 102. Slurry dispense arm 107 dispenses a flow of slurry onto polishing pad 102.
CMP is the preferred method of obtaining full wafer planarization, as described above, and is currently the only technique capable of over millimeter scale planarization after polishing. Hence, CMP is increasingly being used for planarizing dielectrics and other layers, particularly for applications using 0.35 μm and smaller semiconductor fabrication process technologies. Such applications include, for example, using CMP to planarize the trench oxide fill for a shallow trench isolation process.
As applications for CMP continue to increase, the specific CMP performance requirements for the individual process steps demand a specific set of process conditions and consumables (e.g., polishing slurry, polishing agents, and the like). Additionally, as semiconductor fabrication technology advances, many process requirements (such as global planarity, non-uniformity, edge exclusion, and the like) become increasingly stringent. These conditions often require unique optimization of process conditions. For example. CMP performance requirements are even more stringent with sub-0.35 μm semiconductor fabrication process technologies. The narrowing depth of focus at such resolutions requires optimal planarization performance from the CMP process.
One method of optimizing the CMP process for the differing devices is to have a uniquely optimized CMP machine for each particular device being fabricated. With individual, uniquely optimized CMP machines, the variables of the CMP process can be finely tuned for the requirements of the particular device being fabricated. Wafers containing devices of one type are thereby uniquely polished in relation to wafers containing devices of another type.
It is possible to use multiple individually tailored CMP machines or even a single CMP machine with multiple individually tailored polishing platens. Such machines, however, are not practical. The capitol equipment costs, wafer throughput, fabrication facility floor space requirements, and operator training expenses of such machines each tend to outweigh the achievable benefits.
Thus, what is required is a system which can be readily optimized for differing CMP process requirements. The required system should be readily tunable for differing devices being polished. The required system should be tailorable, depending upon the requirements of the particular devices being polished, without adversely impacting wafer throughput. Additionally, the required system should have minimal added capitol equipment costs, should not require increased fabrication facility floor space, or adversely impact operator training expenses. The present invention provides a novel solution to the above requirements.